1. Field of the Invention
The present invention relates to a power semiconductor device and a method for manufacturing the same, and more particularly to a technique for suppressing a leak current to improve electric characteristics such as a main breakdown voltage and a gate-oxide-film breakdown voltage in a power semiconductor device such as a diode and a power MOSFET.
2. Description of the Background Art
In power semiconductor devices such as vertical power MOSFETs and horizontal power MOSFETs, where high voltage is applied and large current flows. These devices generally include a semiconductor substrate having a surface epitaxial growth layer having a transistor formed inside.
FIG. 14 is a cross section showing a background-art structure of a vertical MOSFET with trench gate as an example of the power semiconductor device.
As shown in FIG. 14, an epitaxial growth layer 102 having an n-type impurity and a diffusion layer 103 having a p-type impurity are formed in sequence on a surface of a n.sup.+ semiconductor substrate 101.
Further, a trench which is deeper than a film thickness of the p-type diffusion layer 103 is formed, extending from a surface of the p-type diffusion layer 103 to the inside of the n-type epitaxial growth layer 102. A source layer 104 having an n-type impurity is formed in a predetermined region of the p-type diffusion layer 103 at an opening corner of the trench, and an oxide film 105 serving as a gate oxide film is formed on a wall surface and a bottom surface inside the trench. Further, the trench is filled with a trench buried layer 110 and the trench buried layer 110 is connected to a gate electrode not shown. An interlayer insulating layer 109 is formed so as to cover an upper surface of the trench buried layer 110 and the gate oxide film 105 near the opening corner of the trench. A source electrode 108 is formed so as to cover the interlayer insulating layer 109 and an exposed surface of the p-type diffusion layer 103.
Next, an operation of the background-art vertical MOSFET of FIG. 14 will be discussed.
First, a positive (forward) drain voltage Vds is applied across a drain electrode 107 and the source electrode 108 by an external power supply. In this state, a positive (forward) gate voltage which exceeds a predetermined gate threshold voltage is applied across the gate electrode not shown and the source electrode 108. At this time, electrons are induced in a region near an interface between the p-type diffusion layer 103 and the gate oxide film 105, to form an n-type channel region. With this channel region, the n-type source layer 104 and the n-type epitaxial growth layer 102 become conducting, and an electronic current flowing in from an external circuit side not shown through the source electrode 108 further flows through the n-type source layer 104, the above channel region in the p-type diffusion layer 103, the n-type epitaxial growth layer 102 and the n-type semiconductor substrate 101 to the drain electrode 107, whereby the device comes into an ON state.
Subsequently, when the gate electrode is changed into a voltage lower than the above gate threshold voltage (reversely biased), the channel region which was inverted into n-type returns to p-type layer to break the above current path, whereby the device comes into an OFF state.
The main breakdown voltage of the power semiconductor device having a vertical MOSFET structure with trench gate depends on the resistivity and the thickness of the epitaxial growth layer. Specifically, when the drain voltage rises in the OFF state, a reverse voltage applied across a pn junction in the interface between the n-type epitaxial growth layer 102 and the p-type diffusion layer 103 rises and at this time a depletion layer in the pn junction extends across the n-type epitaxial growth layer 102 and the p-type diffusion layer 103 to hold the voltage. The breakdown voltage in the pn junction, i.e., the main breakdown voltage depends on an electric field in the depletion layer of the junction and is therefore closely related to the reverse voltage and the width of the depletion layer. Further, the width of the depletion layer depends on the respective impurity concentrations of the n-type epitaxial growth layer 102 and the p-type diffusion layer 103 and the resistivity also depends on the impurity concentration, and therefore the width of the depletion layer depends on the resistivity of the epitaxial growth layer. When the epitaxial growth layer does not have enough thickness relative to the extension of the depletion layer, it is impossible to determine large breakdown voltage in the pn junction. Therefore, the main breakdown voltage in the power semiconductor device having the above structure depends on the resistivity and the thickness of the epitaxial growth layer.
In the vertical MOSFET with trench gate of FIG. 14, (i) there occurs metal contamination in the semiconductor device due to some dust and the like from a manufacturing apparatus. Further, (ii) there occurs a crystal defect inside the epitaxial growth layer due to damages in both trench formation and formation of films such as an SiO.sub.2 film and further due to damage in wafer processing such as dry etching and the like. The metal contamination and the crystal defect cause the following problems.
1 First, the crystal defect of (ii) forms a deep energy level between energy bandgaps of the epitaxial growth layer resulting in a leak current produced by recombination. Also the impurities of heavy metals such as Fe and Cu of (i) are trapped by the above crystal defect, to cause the leak current. In other words, there arises a problem of increasing the leak current between the drain and source as indicated by a curve .alpha. in FIG. 15 due to the above causes.
2 Moreover, generation of the leak current means deterioration in reverse bias characteristics, such that if the leak current greatly increases, the main breakdown voltage decreases as indicated by a curve .beta. in FIG. 15, causing a problem that desired electric characteristics can not be obtained.
3 The above-noted crystal defect is likely to appear near the interface between the gate oxide film inside the trench and the epitaxial growth layer in the manufacturing process. Therefore, a stress is likely to be generated near the interface, and distortion due to the stress causes deterioration in insulativeness of the gate oxide film. The deterioration in film quality (insulativeness) of the gate oxide film lowers the range of voltage applicable to the gate oxide film (deterioration in gate-oxide-film breakdown-voltage characteristics) as shown in FIG. 16, and, again, the desired electric characteristics can not be obtained.
Suppressing the above problem sources (i) and (ii) which causes the problems 1 to 3 is strongly required in the technical field of the vertical MOSFET.
These problems are not limited to the technical field of the vertical MOSFET. Specifically, also in a diode, a thyristor having the pn junction and the like, through the junction face reversely biased by the above problem sources (i) and (ii), 1 the leak current is generated in a bulk and 2 when the leak current is of a high value, the main breakdown voltage is deteriorated. Further, also in the vertical MOSFET with plane gate, the problems 1 and 2 are caused, and the problem sources (i) and (ii) must be resolved. In other words, power semiconductor devices are prone to problems caused by problem sources (i) and (ii) which must be resolved to ensure the desired electric characteristics.
On the other hand, prior art attempts at removing the crystal defect problems are disclosed relative to a horizontal MOSFET in a CMOS device. See, for example Japanese Patent Application Laid Open Gazette 57-5364. The technique in this document relates to a MOS integrated circuit device having a silicon monocrystalline substrate, and an appropriate range of oxygen concentration is specified from a relation between an oxygen concentration of the substrate and a leak-current characteristic failure rate of the MOS integrated circuit.
In a technique disclosed in Japanese Patent Application Laid Open Gazette 61-3415, an appropriate range of concentration of oxygen and carbon in the silicon substrate is specified to suppress electric characteristic failure such as the leak current and hold failure in a dynamic MOS memory.
It is noted that the problems 1 to 3 pointed out by the present inventors relate to a power semiconductor device to control a bulk current as a main current. In this power semiconductor device, it is considered that the bulk has a great effect on the main current, and without this consideration, it seems impossible to overcome all the problems 1 to 3. In these prior-art documents, the appropriate oxygen concentration is specified in the integrated circuit device having a structure where an integrated circuit is formed in a silicon substrate surface and a surface current flows only in the substrate surface, i.e., a horizontal (planar) MOS structure, and no teaching or suggestion is made to the effect of the bulk on characteristics. Therefore, it is not believed that the prior-art documents can be adopted to solve the above problems 1 to 3.
Thus, proposing a new structure to overcome the problems 1 to 3 in the power semiconductor device is an urgent matter.